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Espressif Systems /ESP32-H2 /PCR /PWM_CLK_CONF

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Interpret as PWM_CLK_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PWM_DIV_NUM0PWM_CLKM_SEL 0 (PWM_CLKM_EN)PWM_CLKM_EN

Description

PWM_CLK configuration register

Fields

PWM_DIV_NUM

The integral part of the frequency divider factor of the pwm function clock.
PWM_CLKM_SEL

set this field to select clock-source. 0(default): do not select anyone clock, 1: 160MHz, 2: XTAL, 3: FOSC.
PWM_CLKM_EN

set this field as 1 to activate pwm clkm.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data